TransEDA Announces Support of Embedded PSL for VHDL, Verilog and Mixed-Language Designs
Eastleigh UK - Paris France, November 15, 2004 – TransEDA, a leader in coverage and verification
solutions, announces the availability of version 2.5 of its imPROVE-HDL formal property checker.
This new version brings many improvements to enable the easy deployment of Assertion-Based
Verification (ABV) methodologies for complex SoC designs.
In addition to reading PSL assertions from an external file, imPROVE-HDL v2.5 now supports PSL in
both VHDL and Verilog flavors embedded in the design. Among the tool’s improvements, early
customers have also reported a performance increase of 25% in average.
Powered by the PSL technology, originally based on the Sugar language developed by IBM Research,
the extension of PSL support in TransEDA’s imPROVE-HDL formal property checker enables
engineers to exhaustively verify the PSL assertions embedded in their RTL code, hence
complementing the dynamic verification of these assertions using a simulator. This new capability
gives designers and verification engineers a seamless access to two different and complementary
verification methods based on the same PSL assertions, to increase verification observability and
productivity.
Another benefit of imPROVE-HDL is its ability to quickly debug the assertions’ behavior. The tool
automatically computes the shortest test sequence leading to the origin of a failing property, or
exhaustively verifies that a given assertion is always true. Moreover, using VN-Spec – TransEDA’s
unique Requirements Traceability solution - verification engineers can easily correlate assertion
verification results output from imPROVE-HDL with their test plans, test benches and even with the
original specification.
Verification engineers can also use the imPROVE-HDL technology in conjunction with TransEDA’s
Hardware Protocol Kits (HPKs) to automatically and exhaustively verify the protocol layer and the
functional performance of their AMBA and OCP based designs.
“The growing adoption for PSL across the industry is a very positive trend for design and verification
engineers”, said Yaron Wolfsthal, Manager of Formal Verification and Testing Technologies at the
IBM Haifa Research Lab. “This trend and support for PSL from companies like TransEDA, gives
engineers more weight to meet the SoC verification challenge.”
“This announcement shows our commitment to integrate standard languages into our tools for the
benefit of our customers”, adds Modesto Casas, Head of Worldwide Marketing and Sales at
TransEDA. “With this PSL support we now offer our customers a smooth path to deploy Assertion-
Based Verification methodologies and to seamlessly integrate formal assertion checking within their
current verification flows.”
imPROVE-HDL Formal Property Checker
TransEDA’s imPROVE-HDL is a formal property checker that increases productivity of SoC
verification by complementing traditional simulation. Unlike dynamic assertion checking or random
test generation techniques, it performs exhaustive debugging of RTL models without using test
benches.
imPROVE-HDL finds the difficult-to-reach bugs hidden in complex protocol or control
implementations and helps identify and fix ambiguities in specifications. The tool easily fits into
assertion-based verification (ABV) methodologies and enables to dramatically reduce design
verification time. Assertions are read from many of the popular property languages and shared with
simulation, making the benefits of imPROVE-HDL available with no additional effort.
About TransEDA
TransEDA is a leader in coverage and ready-to-use verification solutions for electronic designs. The
company has over ten years of operating experience in the EDA market.
TransEDA provides advanced verification products for simulation platforms including coverability
analysis capability, specification coverage and impact analysis, configurable HDL rule checking, static
assertion verification, static bus controller coverage, verification IP, bus-based system-level test
automation, test suite optimization, and transistor-level functional abstraction.
TransEDA is part of the Valiosys Group and has offices in North America, Europe and Japan, and
local representatives in Singapore, China, Korea and Taiwan. For more information, visit
www.transeda.com.
For more information, please contact:
Sophie Gosselin
TransEDA - Valiosys Group
Phone: +33 153 384 600
Email: sophie.gosselin@transeda.com
